Advanced computer architecture : (Record no. 2395)

000 -LEADER
fixed length control field 02540nam a22002417a 4500
003 - CONTROL NUMBER IDENTIFIER
control field OSt
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20131225150431.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 130330t20122000ii.ill.g |||| 001 0 eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9780070702103 (pbk)
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 0070702101 (pbk)
040 ## - CATALOGING SOURCE
Transcribing agency NCL
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 005.35
Item number HWA-A 2012 3492
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Hwang, Kai
9 (RLIN) 863
245 1# - TITLE STATEMENT
Title Advanced computer architecture :
Remainder of title parallelism, scalability, programmability /
Statement of responsibility, etc. by Kai Hwang and Naresh Jotwani
250 ## - EDITION STATEMENT
Edition statement 2nd ed.
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication, distribution, etc. New Delhi ;
Name of publisher, distributor, etc. McGraw Hill Private Limited,
Date of publication, distribution, etc. 2012, 2000c
300 ## - PHYSICAL DESCRIPTION
Extent viii, 723 p. :
Other physical details ill. ;
Dimensions 24 cm.
500 ## - GENERAL NOTE
General note Index included
505 ## - FORMATTED CONTENTS NOTE
Formatted contents note 5.4. Sequential and Weak Consistency Models. Ch. 6. Pipelining and Superscalar Techniques. 6.1. Linear Pipeline Processors. 6.2. Nonlinear Pipeline Processors. 6.3. Instruction Pipeline Design. 6.4. Arithmetic Pipeline Design. 6.5. Superscalar and Superpipeline Design -- pt. III. Parallel and Scalable Architectures. Ch. 7. Multiprocessors and Multicomputers. 7.1. Multiprocessor System Interconnects. 7.2. Cache Coherence and Synchronization Mechanisms. 7.3. Three Generations of Multicomputers. 7.4. Message-Passing Mechanisms. Ch. 8. Multivector and SIMD Computers. 8.1. Vector Processing Principles. 8.2. Multivector Multiprocessors. 8.3. Compound Vector Processing. 8.4. SIMD Computer Organizations. 8.5. The Connection Machine CM-5. Ch. 9. Scalable, Multithreaded, and Dataflow Architectures. 9.1. Latency-Hiding Techniques. 9.2. Principles of Multithreading. 9.3. Fine-Grain Multicomputers. 9.4. Scalable and Multithreaded Architectures. 9.5. Dataflow and Hybrid Architectures. pt. IV. Software for Parallel Programming. Ch. 10. Parallel Models, Languages, and Compilers. 10.1. Parallel Programming Models. 10.2. Parallel Languages and Compilers. 10.3. Dependence Analysis of Data Arrays. 10.4. Code Optimization and Scheduling. 10.5. Loop Parallelization and Pipelining. Ch. 11. Parallel Program Development and Environments. 11.1. Parallel Programming Environments. 11.2. Synchronization and Multiprocessing Modes. 11.3. Shared-Variable Program Structures. 11.4. Message-Passing Program Development. 11.5. Mapping Programs onto Multicomputers. Ch. 12. UNIX, Mach, and OSF/1 for Parallel Computers. 12.1. Multiprocessor UNIX Design Goals. 12.2. Master-Slave and Multithreaded UNIX. 12.3. Multicomputer UNIX Extensions. 12.4. Mach/OS Kernel Architecture. 12.5. OSF/1 Architecture and Applications.
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer Architecture
9 (RLIN) 163
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Jotwani, Naresh
9 (RLIN) 864
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme
Koha item type Books
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Home library Current library Shelving location Date acquired Source of acquisition Inventory number Total Checkouts Full call number Barcode Date last seen Price effective from Koha item type
          Namal Library Namal Library Computer Science 12/25/2013 Allied Book Company Bill no.2984   005.35 HWA-A 2012 3492 0003492 12/25/2013 12/25/2013 Books