MARC details
| 000 -LEADER |
|---|
| fixed length control field |
01237mam a2200277 a 4500 |
| 001 - CONTROL NUMBER |
|---|
| control field |
2258422 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20140224112911.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
981203s20132006ii a g b 001 0 eng |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
|---|
| LC control number |
98050400 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9788177584742(pbk) |
| 040 ## - CATALOGING SOURCE |
|---|
| Transcribing agency |
NCL |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.39 |
| Item number |
MAZ-G 2013 3546 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Mazumder, Pinaki. |
| 245 1# - TITLE STATEMENT |
|---|
| Title |
Genetic algorithms for VLSI design, layout & test automation / |
| Statement of responsibility, etc. |
By Pinaki Mazumder, Elizabeth M. Rudnick. |
| 246 14 - VARYING FORM OF TITLE |
|---|
| Title proper/short title |
Genetic algorithms for VLSI design, layout and test automation / |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Place of publication, distribution, etc. |
New Delhi : |
| Name of publisher, distributor, etc. |
Pearson, |
| Date of publication, distribution, etc. |
2013 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
v, 338 p. : |
| Other physical details |
ill. ; |
| Dimensions |
25 cm. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc |
Includes bibliographical references (p. 314-331) and index. |
| 505 00 - FORMATTED CONTENTS NOTE |
|---|
| Miscellaneous information |
1. |
| Title |
Introduction -- |
| Miscellaneous information |
2. |
| Title |
Partitioning -- |
| Miscellaneous information |
3. |
| Title |
Standard Cell and Macro Cell Placement -- |
| Miscellaneous information |
4. |
| Title |
Macro Cell Routing -- |
| Miscellaneous information |
5. |
| Title |
FPGA Technology Mapping -- |
| Miscellaneous information |
6. |
| Title |
Automatic Test Generation -- |
| Miscellaneous information |
7. |
| Title |
Peak Power Estimation -- |
| Miscellaneous information |
8. |
| Title |
Parallel Implementations -- |
| Miscellaneous information |
9. |
| Title |
Conclusion. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Integrated circuits |
| General subdivision |
Very large scale integration |
| -- |
Design and construction. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Integrated circuits |
| General subdivision |
Very large scale integration |
| -- |
Testing. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Genetic algorithms. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Rudnick, Elizabeth M. |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
|
| Koha item type |
Books |
