Digital system test and testable design : using HDL models and architectures /

index included

CONTENTS
Chapter 1: Basic of tests and role of HDL's
Chapter 2: Verilog HDL for design and test
Chapter 3: fault and defect modeling
Chapter 4: Fault simulation applications and methods
Chapter 5: Test pattern generation methods and algorithm
Chapter 6: Deterministic test generation algorithm
Chapter 7: Design for test by means of scan
Chapter 8: standard IEEE test access methods
Chapter 9: Logic built in self test
Chapter 10: Test compression
Chapter 11: Memory testing by means of memory BIST

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Annotation This book is about digital system testing and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms.Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware/software environment facilitates description of complex test programs and test strategies.

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