VHDL : programming by example / by Douglas L Perry

By: Perry, Douglas LMaterial type: TextTextPublication details: New Delhi : McGraw-Hill, 2013Edition: 4th EditionDescription: xvii, 476 p: ill; 28 cm.+ 1 Compact Disc (4 3/4 in.)ISBN: 9780070499447 (pbk)Subject(s): VHDL (Computer hardware description language) | COMPUTERS -- Machine Theory | COMPUTERS -- Computer EngineeringDDC classification: 621.392
Contents:
Foreword Preface Acknowledgments Chapter 1: Introduction to VHDL Chapter 2: Behavioral Modeling Chapter 3: Sequential Processing Chapter 4: Data Types Chapter 5: Subprograms and Packages Chapter 6: Predefined Attributes Chapter 7: Configurations Chapter 8: Advanced Topics Chapter 9: Synthesis Chapter 10: VHDL Systems Chapter 11: High Level Design Flow Chapter 12: Top-Level System Design Chapter 13: CPU: Synthesis Description Chapter 14: CPU: RTL Simulation Chapter 15: CPU Design: Synthesis Results Chapter 16: Place and Route Chapter 17: CPU: VITAL Simulation Chapter 18: At Speed Debugging Techniques Appendix A: Standard Logic Package Appendix B: VHDL Reference Tables Appendix C: Reading VHDL BNF Appendix D: VHDL93 Updates Index About the Author
Summary: User's guide to VHDL reflecting the very latest design methods.
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621.392 PAL-V 2011 4559 Verilog HDL : a guide to digital design and synthesis / 621.392 PER-V 2013 2178 VHDL : 621.392 PER-V 2013 4001 VHDL : 621.392 PER-V 2013 8972 VHDL : 621.395 CIL-A 2003 3306 Advanced digital design with the Verilog HDL/ 621.395 RAM-D 2011 1124 Digital VLSI systems design : 621.395 ROB-D 2001 10090 Digital design with CPLD applications and VHDL /

Includes index.

Foreword Preface Acknowledgments Chapter 1: Introduction to VHDL Chapter 2: Behavioral Modeling Chapter 3: Sequential Processing Chapter 4: Data Types Chapter 5: Subprograms and Packages Chapter 6: Predefined Attributes Chapter 7: Configurations Chapter 8: Advanced Topics Chapter 9: Synthesis Chapter 10: VHDL Systems Chapter 11: High Level Design Flow Chapter 12: Top-Level System Design Chapter 13: CPU: Synthesis Description Chapter 14: CPU: RTL Simulation Chapter 15: CPU Design: Synthesis Results Chapter 16: Place and Route Chapter 17: CPU: VITAL Simulation Chapter 18: At Speed Debugging Techniques Appendix A: Standard Logic Package Appendix B: VHDL Reference Tables Appendix C: Reading VHDL BNF Appendix D: VHDL93 Updates Index About the Author

User's guide to VHDL reflecting the very latest design methods.

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