VLSI test principles and architectures : design for testability / edit by Laung-Terng Wang
Material type: TextPublication details: New Delhi : Morgan Kaufmann, 2011cDescription: xxx, 777 p. : ill. ; 25cmISBN: 9780123705976 (pbk)Subject(s): Integrated circuits -- Very large scale integrationDDC classification: 621.39Item type | Current library | Call number | Copy number | Status | Date due | Barcode | Item holds |
---|---|---|---|---|---|---|---|
Books | Namal Library Electrical Engineering | 621.39 WAN-V 21011 1149 (Browse shelf (Opens below)) | 1 | Available | 1149 | ||
Books | Namal Library Electrical Engineering | 621.39 VLS- 2013 4024 (Browse shelf (Opens below)) | 2 | Available | 0004024 |
Index included
Chapter 1 Introduction -- Chapter 2 Design for Testability -- Chapter 3 Logic and Fault Simulation -- Chapter 4 Test Generation -- Chapter 5 Logic Built-In Self-Test -- Chapter 6 Test Compression -- Chapter 7 Logic Diagnosis -- Chapter 8 Memory Testing and Built-In Self-Test -- Chapter 9 Memory Diagnosis and Built-In Self-Repair -- Chapter 10 Boundary Scan and Core-Based Testing -- Chapter 11 Analog and Mixed-Signal Testing -- Chapter 12 Test Technology Trends in the Nanometer Age.
This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in
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