TY  - BOOK
AU  - Mano,M.Morris
TI  - Digital design
SN  - 0130621218
U1  - 621.381537 
PY  - 2002///
CY  - Upper Saddle River, NJ
PB  - Prentice-Hall
KW  - Electronic digital computers
KW  - Circuits
KW  - Logic circuits
KW  - Logic design
KW  - Digital integrated circuits
N1  - Index included; Includes bibliographical references and index; 1; Binary Systems --; 1-1; Digital Computers and Digital Systems --; 1-2; Binary Numbers --; 1-3; Number Base Conversions --; 1-4; Octal and Hexadecimal Numbers --; 1-5; Complements --; 1-6; Signed Binary Numbers --; 1-7; Binary Codes --; 1-8; Binary Storage and Registers --; 1-9; Binary Logic --; 2; Boolean Algebra and Logic Gates --; 2-1; Basic Definitions --; 2-2; Axiomatic Definition of Boolean Algebra --; 2-3; Basic Theorems and Properties of Boolean Algebra --; 2-4; Boolean Functions --; 2-5; Canonical and Standard Forms --; 2-6; Other Logic Operations --; 2-7; Digital Logic Gates --; 2-8; Integrated Circuits --; 3; Simplification of Boolean Functions --; 3-1; The Map Method --; 3-2; Two- and Three-Variable Maps --; 3-3; Four-Variable Map --; 3-4; Five-Variable Map --; 3-5; Product of Sums Simplification --; 3-6; NAND and NOR Implementation --; 3-7; Other Two-Level Implementations --; 3-8; Don't-Care Conditions --; 3-9; The Tabulation Method --; 3-10; Determination of Prime Implicants --; 3-11; Selection of Prime Implicants --; 3-12; Concluding Remarks --; 4; Combinational Logic --; 4-1; Introduction --; 4-2; Design Procedure --; 4-3; Adders --; 4-4; Subtractors --; 4-5; Code Conversion --; 4-6; Analysis Procedure --; 4-7; Multilevel NAND Circuits --; 4-8; Multilevel NOR Circuits --; 4-9; Exclusive-OR Functions --; 5; MSI and PLD Components --; 5-1; Introduction --; 5-2; Binary Adder and Subtractor --; 5-3; Decimal Adder --; 5-4; Magnitude Comparator --; 5-5; Decoders and Encoders --; 5-6; Multiplexers --; 5-7; Read-Only Memory (ROM) --; 5-8; Programmable Logic Array (PLA) --; 5-9; Programmable Array Logic (PAL) --; 6; Synchronous Sequential Logic --; 6-1; Introduction --; 6-2; Flip-Flops --; 6-3; Triggering of Flip-Flops --; 6-4; Analysis of Clocked Sequential Circuits --; 6-5; State Reduction and Assignment --; 6-6; Flip-Flop Excitation Tables --; 6-7; Design Procedure --; 6-8; Design of Counters --; 7; Registers, Counters, and the Memory Unit --; 7-1; Introduction --; 7-2; Registers --; 7-3; Shift Registers --; 7-4; Ripple Counters --; 7-5; Synchronous Counters --; 7-6; Timing Sequences --; 7-7; Random-Access Memory (RAM) --; 7-8; Memory Decoding --; 7-9; Error-Correcting Codes --; 8; Algorithmic State Machines (ASM) --; 8-1; Introduction --; 8-2; ASM Chart --; 8-3; Timing Considerations --; 8-4; Control Implementation --; 8-5; Design with Multiplexers --; 8-6; PLA Control --; 9; Asynchronous Sequential Logic --; 9-1; Introduction --; 9-2; Analysis Procedure --; 9-3; Circuits with Latches --; 9-4; Design Procedure --; 9-5; Reduction of State and Flow Tables --; 9-6; Race-Free State Assignment --; 9-7; Hazards --; 9-8; Design Example --; 10; Digital Integrated Circuits --; 10-1; Introduction --; 10-2; Special Characteristics --; 10-3; Bipolar-Transistor Characteristics --; 10-4; RTL and DTL Circuits --; 10-5; Transistor-Transistor Logic (TTL) --; 10-6; Emmitter-Coupled Logic (ECL) --; 10-7; Metal-Oxide Semiconductor (MOS) --; 10-8; Complementary MOS (CMOS) --; 10-9; CMOS Transmission Gate Circuits --; 11; Laboratory Experiments --; 11-0; Introduction to Experiments --; 11-1; Binary and Decimal Numbers --; 11-2; Digital Logic Gates --; 11-3; Simplification of Boolean Functions --; 11-4; Combinational Circuits --; 11-5; Code Converters --; 11-6; Design with Multiplexers --; 11-7; Adders and Subtractors --; 11-8; Flip-Flops --; 11-9; Sequential Circuits --; 11-10; Counters --; 11-11; Shift Registers --; 11-12; Serial Addition --; 11-13; Memory Unit --; 11-14; Lamp Handball --; 11-15; Clock-Pulse Generator --; 11-16; Parallel Adder --; 11-17; Binary Multiplier --; 11-18; Asynchronous Sequential Circuits --; 12; Standard Graphic Symbols --; 12-1; Rectangular-Shape Symbols --; 12-2; Qualifying Symbols --; 12-3; Dependency Notation --; 12-4; Symbols for Combinational Elements --; 12-5; Symbols for Flip-Flops --; 12-6; Symbols for Registers --; 12-7; Symbols for Counters --; 12-8; Symbol for RAM --; Appendix; Answers to Selected Problems
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