TY  - BOOK
AU  - Wang, Laung-Terng
TI  - VLSI test principles and architectures: design for testability 
SN  - 9780123705976 (pbk)
U1  - 621.39 
PY  - 2011///c
CY  - New Delhi
PB  - Morgan Kaufmann
KW  - Integrated circuits
KW  - Very large scale integration
N1  - Index included; Chapter 1 Introduction -- Chapter 2 Design for Testability -- Chapter 3 Logic and Fault Simulation -- Chapter 4 Test Generation -- Chapter 5 Logic Built-In Self-Test -- Chapter 6 Test Compression -- Chapter 7 Logic Diagnosis -- Chapter 8 Memory Testing and Built-In Self-Test -- Chapter 9 Memory Diagnosis and Built-In Self-Repair -- Chapter 10 Boundary Scan and Core-Based Testing -- Chapter 11 Analog and Mixed-Signal Testing -- Chapter 12 Test Technology Trends in the Nanometer Age
N2  - This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in
ER  -