000 00786cam a22002534a 4500
001 15889404
003 OSt
005 20140224155113.0
008 090901s20132010ii a g b 001 0 eng
010 _a 2009034771
020 _a9788131755020(pbk)
040 _cNCL
082 0 0 _a621.390
_bZWO-D 2013 3554
100 1 _aZwolinski, Mark.
245 1 _aDigital system design with SystemVerilog /
_cby Mark Zwolinski.
260 _aNew Delhi :
_bPearson,
_c2013
300 _av, 367p. :
_bill. ;
_c24 cm.
500 _aindex present
504 _aIncludes bibliographical references and index.
650 0 _aVerilog (Computer hardware description language)
650 0 _aElectronic digital computers
_xDesign and construction.
650 0 _aComputer simulation.
942 _2ddc
_cBK
999 _c2558
_d2558