000			01563nam a22002177a 4500
003			LSCPL
005			20140204105830.0
008			130607t2011 ii.ill.g |||| 001 0 eng d
020			_a9780123705976 (pbk)
040			_cNCL
082			_a621.39 _bWAN-V 21011 1149
245	1		_aVLSI test principles and architectures : _bdesign for testability / _cedit by Laung-Terng Wang
260			_aNew Delhi : _bMorgan Kaufmann, _c2011c.
300			_axxx, 777 p. : _b ill. ; _c25cm.
500			_aIndex included
505			_aChapter 1 Introduction -- Chapter 2 Design for Testability -- Chapter 3 Logic and Fault Simulation -- Chapter 4 Test Generation -- Chapter 5 Logic Built-In Self-Test -- Chapter 6 Test Compression -- Chapter 7 Logic Diagnosis -- Chapter 8 Memory Testing and Built-In Self-Test -- Chapter 9 Memory Diagnosis and Built-In Self-Repair -- Chapter 10 Boundary Scan and Core-Based Testing -- Chapter 11 Analog and Mixed-Signal Testing -- Chapter 12 Test Technology Trends in the Nanometer Age.
520			_aThis book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in
650		0	_aIntegrated circuits _xVery large scale integration _91636
700			_aWang, Laung-Terng _91745
942			_2ddc _cBK
999			_c811 _d811