MARC details
| 000 -LEADER |
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| fixed length control field |
04645nam a22003012 b4500 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20200127023250.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
131225b2002 ii ||||g |||| 001 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| Canceled/invalid ISBN |
9788181474643 (pbk) |
| 040 ## - CATALOGING SOURCE |
|---|
| Transcribing agency |
NCL |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.3 |
| Item number |
CRO-N 2002 3299 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Crowley, Patrick, |
| Dates associated with a name |
1974-, |
| Relator term |
author. |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Network Processor Design : |
| Remainder of title |
Vol. 2: Issues and Practices/ |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Name of publisher, distributor, etc. |
Morgan Kaufmann [Imprint] |
| Date of publication, distribution, etc. |
2002c |
| Place of publication, distribution, etc. |
San Diego : |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
(464 p.) : |
| Other physical details |
ill. ; |
| Dimensions |
24 cm |
| 490 1# - SERIES STATEMENT |
|---|
| Series statement |
The Morgan Kaufmann Series in Computer Architecture and Design Ser. |
| 500 ## - GENERAL NOTE |
|---|
| General note |
Index present |
| 505 ## - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
1: Network Processors: Themes and challenges<br/>2: A programmable, Scalable platform for next generation networking<br/>3: Power consideration in network processor design<br/>4: Worst - case execution time estimation for hardware - assisted multithreaded processors<br/>5: Multiprocessor scheduling in processor - based router platforms : issues and ideas<br/>6: A massively multithreaded packet processor <br/>7: Exploring trade - offs in performance and programmability of processing element toplogies for network processor<br/>8: Packet classification and termination in aprotocol processor<br/>9: NP- click : A programming model for the intel IXP1200<br/>10: NEPAL: A framework for efficiently structuring applications for network processors<br/>11: Efficient and faithful performance modeling for network-processor-based system designs<br/>12: High-speed legitimacy- based DDoS packet filtering with network processors: A case study and implementation on the intel IXP1200<br/>13: Directions in packet classification for network processors<br/>14: Implementing high- performance, high-value traffic management using agere network processor solutions<br/>15: AMCC nPcore NISC Architecture<br/>16: Adaptable bandwidth allocation for QoS support in network processor<br/>17: IDT network search engine with QDR LA-1 interface <br/>18: Implementing voice over AAL2 on a network processor<br/>19: Implementing QoS mechanisms on the motorola C-Port C-5e network processor<br/>20: A c-Based programming language for multiprocessor network SoC architectures<br/> |
| 506 ## - RESTRICTIONS ON ACCESS NOTE |
|---|
| Terms governing access |
Available for distribution in: UNITED KINGDOM, USA, SOUTH AFRICA, AUSTRALIA, NEW ZEALAND |
| 520 8# - SUMMARY, ETC. |
|---|
| Summary, etc. |
Annotation |
| Expansion of summary note |
<p><br />As the demand for digital communication networks has increased, so have the challenges in network component design. To meet ever-escalating performance, flexibility, and economy requirements, the networking industry has opted to build products around network processors. These new chips range from task-specific processors, such as classification and encryption engines, to more general-purpose packet or communications processors. Programmable yet application-specific, their designs are tailored to efficiently implement communications applications such as routing, protocol analysis, voice and data convergence, firewalls, VPNs, and QoS.<br /></p><p><br />Network processor design is an emerging field with issues and opportunities both numerous and formidable. To help meet this challenge, the editors of this volume created the first Workshop on Network Processors, a forum for scientists and engineers from academia and industry to discuss their latest research in the architecture, design, programming, and use of these devices. In addition to including the results of the Workshop in this volume, the editors also present specially commissioned material from practicing designers, who discuss their companies' latest network processors. <i>Network Processor Design: Issues and Practices</i> is an essential reference on network processors for graduate students, researchers, and practicing designers.<br /><br />* Includes contributions from major academic and industrial research labs including Aachen University of Technology; Cisco Systems; Infineon Technologies; Intel Corp.; North Carolina State University; Swiss Federal Institute of Technology; University of California, Berkeley; University of Dortmund; University of Washington; and Washington University.<br />* Examines the latest network processors from Agere Systems, Cisco, IBM, Intel, Motorola, Sierra Inc., and TranSwitch.</p> |
| 521 ## - TARGET AUDIENCE NOTE |
|---|
| Target audience note |
Scholarly & Professional |
| Source |
Elsevier Science & Technology Books |
| 655 #7 - INDEX TERM--GENRE/FORM |
|---|
| Genre/form data or focus term |
Electronic books. |
| Source of term |
lcgft |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Hadimioglu, Haldun, |
| Relator term |
author. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Franklin, Mark, |
| Relator term |
author. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Onufryk, Peter Z., |
| Relator term |
author. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Relationship information |
Print version: |
| Main entry heading |
Crowley, Patrick 1974- Author |
| Title |
Network Processor Design |
| Place, publisher, and date of publication |
Morgan Kaufmann [Imprint], Oct. 2002 ; San Diego : Elsevier Science & Technology Books |
| International Standard Book Number |
9781558608757 |
| -- |
1558608753 |
| Record control number |
(BIP US)007909471 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
|
| Koha item type |
Books |
