VLSI test principles and architectures : (Record no. 811)
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000 -LEADER | |
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fixed length control field | 01563nam a22002177a 4500 |
003 - CONTROL NUMBER IDENTIFIER | |
control field | LSCPL |
005 - DATE AND TIME OF LATEST TRANSACTION | |
control field | 20140204105830.0 |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
fixed length control field | 130607t2011 ii.ill.g |||| 001 0 eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
International Standard Book Number | 9780123705976 (pbk) |
040 ## - CATALOGING SOURCE | |
Transcribing agency | NCL |
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
Classification number | 621.39 |
Item number | WAN-V 21011 1149 |
245 1# - TITLE STATEMENT | |
Title | VLSI test principles and architectures : |
Remainder of title | design for testability / |
Statement of responsibility, etc. | edit by Laung-Terng Wang |
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
Place of publication, distribution, etc. | New Delhi : |
Name of publisher, distributor, etc. | Morgan Kaufmann, |
Date of publication, distribution, etc. | 2011c. |
300 ## - PHYSICAL DESCRIPTION | |
Extent | xxx, 777 p. : |
Other physical details | ill. ; |
Dimensions | 25cm. |
500 ## - GENERAL NOTE | |
General note | Index included |
505 ## - FORMATTED CONTENTS NOTE | |
Formatted contents note | Chapter 1 Introduction -- Chapter 2 Design for Testability -- Chapter 3 Logic and Fault Simulation -- Chapter 4 Test Generation -- Chapter 5 Logic Built-In Self-Test -- Chapter 6 Test Compression -- Chapter 7 Logic Diagnosis -- Chapter 8 Memory Testing and Built-In Self-Test -- Chapter 9 Memory Diagnosis and Built-In Self-Repair -- Chapter 10 Boundary Scan and Core-Based Testing -- Chapter 11 Analog and Mixed-Signal Testing -- Chapter 12 Test Technology Trends in the Nanometer Age. |
520 ## - SUMMARY, ETC. | |
Summary, etc. | This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical term or geographic name as entry element | Integrated circuits |
General subdivision | Very large scale integration |
9 (RLIN) | 1636 |
700 ## - ADDED ENTRY--PERSONAL NAME | |
Personal name | Wang, Laung-Terng |
9 (RLIN) | 1745 |
942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
Source of classification or shelving scheme | |
Koha item type | Books |
Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Source of acquisition | Inventory number | Total Checkouts | Full call number | Barcode | Date last seen | Copy number | Price effective from | Koha item type | Cost, normal purchase price |
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Namal Library | Namal Library | Electrical Engineering | 06/07/2013 | Pak Book Corporation | Bill No. 113B170656-2 | 621.39 WAN-V 21011 1149 | 1149 | 07/18/2013 | 1 | 07/18/2013 | Books | |||||||
Namal Library | Namal Library | Electrical Engineering | 01/29/2014 | Allied Book Company | Bill no. 1538 | 621.39 VLS- 2013 4024 | 0004024 | 01/29/2014 | 2 | 01/29/2014 | Books | 1160.00 |